Digital to Analogue Conversion:

the mcp4275

Lecture 10

Uli Raich

UCC semester 2017/2018

The I2C bus

The I2C bus is an industrial standard 2 wire bus using a data (SDA) and a clock (SCL) line.

Adding Vcc and Gnd we need a mere 4 wires to connect

a I2C device to the Raspberry Pi cobbler

The I2C bus was invented by Philips

Typical I2C connections

Open drain signals

Open drain signals mean that you can pull a line down

but you cannot set it to a high level.

If nobody pulls the line down, then it is at Vcc level,

pulled up by a pull-up register.

Like this the contention problem is solved where one device tries

to set a line to a high level, while another sets it to low,

thus creating a short circuit.

I2C Master and slave

The I2C bus has at least one master (in our case the interface in the

Raspberry Pi’s ARM processor) and several slaves

We have the following I2C slave devices:

• mcp4275 DAC
• bmp180 barometric pressure sensor
• pcf8581 8 bit ADC
• ads115 16 bit ADC
• at24c32 eeprom
• ds1307 real time clock
• mma845x accelerometer
• pcf8574 I/O expander used on the 2-line LCD display

I2C addressing

Since there can be several slaves on the bus there must

be a means of distinguishing them through addressing:

Every I2C slave has a 7 bit address associated with it

Usually this address is determined by the manufacturer but

often there are address pins on the devices allowing the

user to have several devices of the same type on the bus

I2C buses and I2C addresses on the Raspberry Pi

The Raspberry Pi has 2 I2C buses with bus 1 being put onto the cobbler

You can find out the addresses of the I2C slaves are currently

connected with the i2cdetect command

Initiating a I2C transfer

Start stop conditions

The master starts a transfer by creating a

start condition:

• high to low transition on SDA while SCL is high

• stop condition: low to high transition on SDA while SCL is high4

Data transmission

Data are transmitted with the SDA line stable with SCL is high

A write cycle

A write cycle:
After the start condition the device address. The eighth bit, the R/W bit is kept low.

The second data byte is considered the register byte and the last one the data byte
The slave acknowledges each byte transfer.

The read cycle

The read cycle is a bit more complex:

First the master sends the slave address with R/W set to write

Then it sends the register information.

After that another address byte is sent, this time with RW set to read

And finally the slave sends the data. The master still sends the clock but

releases the SDA line allowing the slave to control it